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?2006 device engineering inc page 1 of 11 ds-mw-01066-0 1 rev e 08/25/2006 features ? eight gnd/open discrete inputs o meet electrical requirements for ab d0100 gnd/open discrete input. o hysteresis provides noise immunity o internal pull up resistor with 1ma source current to prevent dry relay contacts. o internal isolation diode o inputs protected from lightning induced transients per do160d, section 22, cat a3 and b3. ? 3-wire serial interface (/cs, clk, do) o direct interface to serial peripheral interface (spi) port. o ttl/cmos compatible inputs and tristate output o 10mhz data rate o serial input to expand shift register ? logic supply voltage (vcc): 3.3v or 5v ? analog supply voltage (vdd): 5v to 18v ? 16l nb soic package ? 16l ceramic so package pin assignments dei1066 1 din1 din2 din3 din4 vdd gnd vcc gnd 16 din5 din6 din7 din8 sdin /cs dout sclk figure 1 dei1066 pin assignment (16 lead nb soic) dei1066 octal gnd/open input, serial output interface ic d evice e ngineering incorporated 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: admin@deiaz.com
?2006 device engineering inc page 2 of 11 ds-mw-01066-0 1 rev e 08/25/2006 functional description the dei1066 is an eight-channel discrete-to digital interface bicmos device. it senses eight ground/open discrete signals of the type commonly found in avionic systems. the data is read from the device via an eight-bit se rial shift register with 3-sta te output. this serial interface is compatible with the i ndustry standard serial peri pheral interface (spi) bus. table 1 pin descriptions pins name description 8-1 din[8:1] parallel data inputs. eight ground/open format discrete signals. these have an internal pull-up to vdd. the logic threshold and hysteresis characteristics are determined by the applied vdd voltage. 9 dout serial data output. this pin is the output from the last stage of the shift register. this is a 3-state output. 10 sclk serial shift clock. a low-to-high transition on this input shifts data on the serial data input into the shift register and data in stage 8 is shifted out dout, being replaced by the data previously stored in stage 7. 11 /cs chip select. a high-to-low transition on this input loads data from the parallel din[8:1] inputs into the shift register. a low level on this input enables the dout 3-state output and th e shift register. a high level on this input forces dout to the high impedance state and disables the shift register so sclk transitions have no effect. 12 sdin serial data input. data on this input is shifted into the shift register on the rising edge of the sclk input if the /cs input is low. this input has an internal pull-down resistor to gnd. 13 gnd logic ground. 14 vcc logic supply voltage. 15 gnd analog ground. 16 vdd analog supply voltage. sdin di1 di2 di3 di4 di5 di6 di7 di8 q8 shift reg sck sh/ld dout scl k / cs sdin input resistors, comparators, filtering, and lightning protection (8 channels) din1 din2 din3 din4 din5 din6 din7 din8 figure 2 dei1066 logic diagram
?2006 device engineering inc page 3 of 11 ds-mw-01066-0 1 rev e 08/25/2006 figure 3 dinn input circuit fi gure 4 din threshold vs vdd table 2 truth table /cs sclk sdin din[8:1] sreg q1 dout 1 x x x x hi-z x x sampled into shift register din1 enabled din8 0 0 x 0 sreg q8 0 1 x 1 sreg q8 0 x x no change no change x x x no change disabled to hi-z din[8:1] input structure each of the eight discrete inputs consist of the circuit shown in figure 3. each dinn signal is conditioned by the resistor / diode network and presented to the comparator in+. the referen ce and hysteresis voltage is developed at the comparator in-. some notable features are: ? when vdd is +15v, the circuit shall source >1ma to a gr ounded input. this current will prevent a ?dry? relay contact. ? the input threshold voltage and hyster esis varies with the vdd supply. o for vdd of +5v, the falling vth > 3.5v. o for vdd of +15v, the rising vth < 14v. o for vdd of +18v, the rising vth < 15.4v. o hysteresis is approximately as shown in figure 4. o the input thresholds vary with vdd supply voltages and can be approximated as follows: for vdd = 5v to 18v ? vlh_max = 0.98*vdd ? 0.65v ? vhl_min = 0.95*vdd ? 0.8v ? the comparator includes an rc filter to provide noise rejection of transient pulses of up to several us. thus there is a relatively large dinx setup time of several us (refer to timing parameter tsu2). ? the inputs can withstand continuous input voltages of 40v minimum. the isolation diode breakdown voltage is greater than 50v. the 12k ohm input resistor is designed to limit diode breakdown current to safe levels during transient events. typical dinn threshold voltage & hystersis 0 2 4 6 8 10 12 14 16 18 0 5 10 15 20 vdd supply voltage (v) din threshold voltage (v) vth+ vth- reference and hysteresis vout (to shift reg) r1 2k r2 12k d1 comparator with rc filter vdd vdd dinn vdd
?2006 device engineering inc page 4 of 11 ds-mw-01066-0 1 rev e 08/25/2006 serial interface and shift register the dei1066 digital interface is an 8-bit serial or parallel -input / serial-output shift register with 3-state output. the control inputs to the shift register ar e connected as shown in figure 2 dei 1066 logic diagram to implement an spi compatible bus consisting of /cs, sclk, dout, and sdin. the figure 5 waveform depicts a typical 8-bit read cycle where the 8 din signals are read on to the serial bus. the figure 6 waveform demonstrates a daisy-chain application where a 16-bit read cycle includes the serial data passed through from the sdin input. /cs sclk dout sdin x x x x din8 din7 din6 din5 din4 din3 din2 din1 din inputs latched in s-reg xx valid din[8:1] figure 5 serial bus read cycle, 8 bit /cs sclk dout sdin si8 si7 si6 si5 si4 si3 si2 si1 x x x x din8 din7 din6 din5 din4 din3 din2 din1 si8 si7 si6 si5 si4 si3 si2 si1 xx valid din[8:1] figure 6 serial bus read cy cle, 16 bit daisy chain
?2006 device engineering inc page 5 of 11 ds-mw-01066-0 1 rev e 08/25/2006 lightning protection dinn inputs are designed to survive lightning induced transients as defined by rtca do160d, section 22, cat a3 and b3, waveforms 3, 4, and 5a, level 3. see waveforms below. figure 7 voltage / current waveform 3 figure 8 voltage waveform 4 waveform source impedance characteristics: ? waveform 3 voc/isc = 600v / 24a => 25 ohms ? waveform 4 voc/isc = 300 v / 60 a => 5 ohms ? waveform 5a voc / isc = 300v / 300a => 1 ohm figure 9 current/voltage waveform 5a t 0 50% peak t1 t2 v t1 = 6.4us t2 = 70us t 0 50% peak t1 t2 v/i t1=40us t2=120us 0 t v/i 25% to 75% of largest peak 50% f = 1mhz and 10mhz
?2006 device engineering inc page 6 of 11 ds-mw-01066-0 1 rev e 08/25/2006 electrical description table 3 absolute maximum ratings parameter min max units vcc supply voltage -0.3 +7.0 v vdd supply voltage -0.3 20 v operating temperature plastic packages ceramic packages -55 -55 +85 +125 c storage temperature plastic packages ceramic packages -55 -65 +150 +150 c input voltage din[8:1] continuous do160d, waveform 3, level 3 do160d, waveform 4 and 5, level 3 logic inputs dout -5 -600 -300 -1.5 -0.5 +40 +600 +300 vcc + 1.5 vcc + 0.5 v v v v v power dissipation @ 85 c: (> 10 sec) 16 lead soic 16 lead csop 0.8 0.53 w w junction temperature: tjmax, plastic packages tjmax, ceramic packages 145 150 c c esd per jedec a114-a human body model logic and supply pins din pins 2000 1000 v lead soldering temperature (10 sec duration) 280 c notes: 1. stresses above absolute maximum ratings may cause permanent damage to the device. 2. voltages referenced to ground table 4 recommended operating conditions parameter symbol conditions supply voltage vcc vdd 5.0v10%, 3.3v10% 5.0 to 18v logic inputs and outputs 0 to vcc discrete inputs din[8:1] 0 to 40v operating temperature plastic ceramic -55 to +85 oc -55 to +125 oc
?2006 device engineering inc page 7 of 11 ds-mw-01066-0 1 rev e 08/25/2006 table 5 dc electrical characteristics limits symbol parameter test conditions vcc (v) ?55 to +85oc -55 to +125oc unit logic inputs and outputs vdd = +5v to +18v v ih min hi level input voltage 3.0 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il max lo level input voltage 3.0 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v ihst min input hysteresis voltage, sclk input (1) 3.0 4.5 5.5 50 50 mv |i out | < 20ua 3.0 4.5 5.5 vcc ? 0.1 vcc ? 0.1 v v oh min hi level output voltage |i out | < 4.5ma 4.5 5.5 3.2 4.5 3.0 4.3 v |i out | < 20ua 3.0 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v ol max low level output voltage |i out | < 4.5ma 4.5 5.5 0.33 0.33 0.40 0.40 v i in max input leakage logic inputs except sdin. sdin vin = vcc or gnd 5.5 5.5 1.0 750 2.0 750 ua i oz max 3-state leakage current output in hi impedance state. 5.5 5.0 10.0 ua discrete inputs vdd = +18v v ih min hi level input voltage 3.0 to 5.5 15.7 15.9 v v il max lo level input voltage 3.0 to 5.5 14.2 14.2 v v ihst min input hysteresis voltage 3.0 to 5.5 1.0 1.0 v i ih max hi level input current vin = 18v vin = 40v 3.0 to 5.5 5 20 10 40 ua i ilmax max lo level input current vin = 0v 3.0 to 5.5 -1.6 -1.6 ma i ilmin min lo level input current vin = 0v 3.0 to 5.5 -1.0 -1.0 ma discrete inputs vdd = +5v v ih min hi level input voltage 3.0 to 5.5 4.35 4.35 v v il max lo level input voltage 3.0 to 5.5 3.53 3.53 v v ihst min input hysteresis voltage 3.0 to 5.5 0.33 0.33 v i ih max hi level input current vin = 18v vin = 40v 3.0 to 5.5 5 20 10 40 ua i ilmax max lo level input current vin = 0v 3.0 to 5.5 -0.5 -0.5 ma i ilmin min lo level input current vin = 0v 3.0 to 5.5 -0.25 -0.25 ma supply voltages vdd = +15v icc max quiescent logic supply current vin(logic) = vcc or gnd vin[8:1] = open 6.0 200 400 ua idd max quiescent analog supply current vin(logic) = vcc or gnd vin[8:1] = open vin[8:1] = gnd 6.0 6.0 11 23 11 24 ma
?2006 device engineering inc page 8 of 11 ds-mw-01066-0 1 rev e 08/25/2006 table 6 ac electrical characteristics limits symbol parameter (4,6 & 7) vcc (v) ?55 to +85oc -55 to +125oc unit f max maximum sclk frequency. (50% duty cycle) (5) maximum usable sclk frequency = 1/(tp2 + tsu3) 2.0 4.5 6.0 2.0 4.5 6.0 4.8 24 28 2.8 10.7 14.6 4.0 20 24 2.2 8.2 11.2 mhz t w minimum sclk pulse width. (50% duty cycle) 2.0 4.5 6.0 100 20 17 120 24 20 ns t su1 minimum setup time, sclk low to /cs . 2.0 4.5 6.0 100 50 40 100 50 40 ns t h1 minimum hold time, /cs to sclk . 2.0 4.5 6.0 20 20 20 20 20 20 ns t su2 setup time, din valid to /cs . (8) 5.0 35 35 us t h2 hold time, /cs to din not valid. (8) 5.0 -1.5 -1.5 us t su3 minimum setup time, sdin valid to sclk . 2.0 4.5 6.0 75 20 15 80 25 15 ns t h3 minimum hold time, sclk to sdin not valid. 2.0 4.5 6.0 5 5 5 5 5 5 ns t p1 maximum propagation delay, /cs to dout valid. (1) 2.0 4.5 6.0 220 55 47 265 72 52 ns t p2 maximum propagation delay, sclk to dout valid. (1) 2.0 4.5 6.0 295 90 70 380 102 75 ns t p3 maximum propagation delay, /cs to dout hi-z. (1) (2) (3) 2.0 4.5 6.0 320 80 59 380 103 77 ns t p4 minimum time between /cs active. 2.0 4.5 6.0 50 25 25 50 25 25 ns c in maximum logic input pin capacitance. (5) 10 10 pf c out maximum dout pin capacitance, output in hi-z state. (5) 15 15 pf 1. dout loaded with 50pf to gnd. 2. dout loaded with 1k ohms to gnd for hi output, 1k ohms to vcc for low output. 3. timing measured at 25%vcc for ?0? to hi-z, 75%vcc for ?1? to hi-z. 4. sample tested on lot basis. 5. not tested 6. unless otherwise noted, vdd=+15v, vil = 0v, vih = vcc 7. measurements made at 50%vcc. 8. vdd = 6v. t su2 represents the maximum possible propagation delay through the input comparator. t h2 represents the minimum possible propagation delay through the input comparator. the negative hold time denotes that din may change prior to /cs and still be valid data at the s-register.
?2006 device engineering inc page 9 of 11 ds-mw-01066-0 1 rev e 08/25/2006 /cs sclk dout sdin din[8:1] t su1 t h1 t w 1/f max t su2 t h2 xx valid t su3 t h3 xx din8 din7 t p1 t p2 t p3 t p4 valid figure 10 switching waveforms
?2006 device engineering inc page 10 of 11 ds-mw-01066- 01 rev e 08/25/2006 package descriptions 16 lead narrow body soic moisture sensitivity: level 2 per je dec j-std-020a (1yr floor life) ja: 73.6 ? c/w (mounted on 4 layer pcb) jc: 29.8 ? c/w pin no 1 7 c h x 45 detail-a detail-a min max soic-16ld symbol millimeters c l c l a a1 b c d e e h h l zd 0.51 ref 0 8 0.41 1.27 5.80 6.20 1.27 bsc 3.81 3.99 9.80 9.98 0.19 0.25 0.36 0.46 0.10 0.25 0.25 0.50 a2 a 1.52 1.72 1.37 1.57 min max soic-16ld symbol inches a1 b c d e e h h l zd .0040 .0098 .014 .018 .0075 .0098 .386 .393 .150 .157 .050 bsc .2284 .2440 .016 .050 0 8 .020 ref .0099 .0196 a2 a .060 .068 .054 .062 a a figure 11 16 lead narrow body soic outline drawing
?2006 device engineering inc page 11 of 11 ds-mw-01066- 01 rev e 08/25/2006 16 lead ceramic small outline package (csop) theta ja: 122 c/w device mounted on 2 layer pcb theta jc: 5 c/w moisture sensitivity level: hermetic figure 12 16 lead csop outline drawing ordering information table 7 part number marking package burn in temperature dei1066-ses dei1066-ses 16 soic no -55 / +85 oc dei1066-sms dei1066-sms 16 soic no -55 / +125 oc DEI1066-SMB DEI1066-SMB 16 soic 96hr / +125 oc -55 / +125 oc dei1066-wms dei1066-wms 16 csop no -55 / +125 oc dei1066-wmb dei1066-wmb 16 csop 96hr / +125 oc -55 / +125 oc dei reserves the right to make changes to any products or sp ecifications herein. dei makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

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